Field of the Invention
The invention relates to an integrated circuit and a method of forming the same, and more particularly, to a semiconductor device and a method of forming the same.
Description of Related Art
In the field of integrated circuit devices, the device dimension is often reduced to ensure high operating speed and low power consumption. However, due to the increasing level of integration of the devices, the minimization of the device dimension reaches its limitations. One proposed solution to overcome the limitations imposed by said device miniaturization is strain engineering.
Strain engineering is to utilize materials with the same crystalline structure but different lattice constants for achieving the purpose of controlling the strain. In most cases, recesses are formed in a substrate beside a gate, and a strain layer is formed in the recesses. If the transistor is an n-type transistor, the strain layer can be a SiC epitaxial layer. If the transistor is a p-type transistor, the strain layer can be a SiGe epitaxial layer. Unfortunately, the integration of the SiGe/SiC strain layer into the CMOS manufacturing process raises certain issues, e.g., in the process of forming the recesses in the substrate beside the gate, the existing spacer cannot effectively block etchant, such that the gate may be damaged.